By Gabriele Manganaro
Have to wake up to hurry fast at the most modern advances in excessive functionality info converters? wish aid picking the easiest structure in your software? With every little thing you must learn about the foremost new converter architectures, this consultant is for you. It offers simple rules, circuit and method layout suggestions and linked trade-offs, casting off long mathematical proofs and supplying intuitive descriptions prematurely. every thing from time-to-digital converters to comparator-based/zero-crossing ADCs is roofed and every subject is brought with a brief precis of the basic fundamentals. useful examples describing genuine chips, in addition to broad comparability among architectural or circuit innovations, ease structure choice and assist you lower layout time and engineering chance. Trade-offs, benefits and drawbacks of every alternative are placed into viewpoint with a dialogue of destiny traits, displaying the place this box is heading, what's riding it and what crucial unanswered questions are.
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Extra info for Advanced data converters
A somewhat arbitrary choice has then been made in the chart shown in Fig. 10, where, similarly to what was done for the ADCs, many classic DAC architectures have been mapped into the BW–SFDR plane. It should also be remarked that the extent of the overlap between some of these architectures is, in actuality, greater than what is depicted. 34 A refresher on the basics Even though distortion (characterized by the SFDR in Fig. 10) is here considered instead of the SNDR, a similar fundamental trade-off between signal frequency and dynamic range of the same nature as Eq.
Furthermore, again both for ADCs and for DACs, step-size errors also lead the transfer characteristic to move away from the ideal straight line. The net deviation of the actual characteristic from such an ideal straight line is quantified by the INL. As the nomenclature of these two errors suggests, the DNL at each step bears no memory of such deviation errors that have occurred at other steps and it is a localized error. On the other hand, the compounding effect of subsequent localized step-size errors, originating from one step to the next one and so on, progressively moves the characteristic away and back from its ideal straight line, hence leading to an integral error that is captured by the INL  (see also the ADC example in Fig.
Individual deviations of each step from the ideal value will lead to localized errors in the characteristic. Such deviations are quantified by the DNL, which specifies how much each step differs from . For example, referring to Fig. 4, let us consider the step width corresponding to Dout = 001. The actual step (solid line) is slightly smaller than the average LSB size. This small negative deviation corresponds to the small negative DNL point on the upper right-hand-side DNL plot. On the other hand, on observing the step width corresponding to Dout = 011, we see that this is considerably larger than the average LSB size, hence leading to a large positive point in the DNL plot for this code.
Advanced data converters by Gabriele Manganaro